DESIGN OF SRAM USING FINFET AND ITS PERFORMANCE ANALYSIS
Research Scholar, Department of Electronics and communication Engineering, Faculty of Engineering & Technology Mansarovar Global University Billkisganj, Sehore, Madhya Pradesh, firstname.lastname@example.org
Dr. Mayank Mathur
Research Guide, Department of Electrical & Electronics Engineering , Faculty of Engineering & Technology Mansarovar Global University, Billkisganj, Sehore, Madhya Pradesh, email@example.com
Due to the loss of channel control, there are several problems with CMOS. Another topic covered in this paper is the impact of FinFET Gate Material Variation on Performance Characteristics. An SRAM cell optimised with FinFET technology is another example. The leakage currents and power dissipation are reduced when MOSFET-based memory arrays are replaced with quasi-planar FinFETs. Stability and area of the SRAM cell are critical design considerations. Fin width and pitch are the primary considerations when it comes to cell optimization. A few of these difficulties include an increase in leakage currents, an increase in on current, and a broad shift in parameter values. FinFET-based SRAM cell optimization was also shown. Fin width and pitch are the primary factors to consider while optimising a cell. High power consumption and an increase in leakage current afflict CMOS-based SRAMs, both of which have a detrimental effect on their performance. The static noise margin affects the cell’s stability. A double-gate n-FinFET is the subject of this paper’s modelling and simulation.
Keywords: SRAM, FINFET, Mosfet, performance, CMOS, IC, Chips, Memory, Power