Abstract

The technology advances from the micron level to the Nanometer level. This striking change in the technology with so many factors might influence the embedded device design and its performance. In the fast-growing technology, it is very difficult to find suitable test method to test embedded SRAM. It is noticed that while going to deep sub-nano technologies, the existing test methods may not fully satisfy the test results due to the increased number of faults and defects. Scale-down technologies have an impact on the parasitic effects also, the parasitic effect creates an additional source of faulty behavior, and making the existing test techniques less effective in detecting them. In this paper we propose a method, taking the parasitic effect into the consideration, which gives the fault information along with its location. In the proposed method we have considered node-to-node open and short defects for different technologies (45nm, 32nm, and 7nm). It is observed that using the proposed test method we have detected existing faults and also undefined faults.

Key Words: Open Faults; Short Faults; Parasitic Extraction Method, Undefined short fault.